Issues

• Compilation issue with aie++

  triSYCL/sycl#236 · Filter by author keryell opened on Aug 17, 2023
  3

  

• xrt_piEventGetProfilingInfo not implemented

  bug
  triSYCL/sycl#224 · Filter by author keryell opened on Apr 7, 2023
  

• Build issue with RHEL8

  bug
  triSYCL/sycl#192 · Filter by author jyoung3131 opened on Jul 15, 2022
  8

  

• There are still some xocc and XOCC in sycl/test/lit.cfg.py

  triSYCL/sycl#188 · Filter by author keryell opened on Jun 21, 2022
  1

  

• Implement USM support for XRT plugin

  enhancement
  triSYCL/sycl#181 · Filter by author keryell opened on May 13, 2022
  3

  

• Is barrier in kernel supported or going to be supported?

  enhancement
  triSYCL/sycl#180 · Filter by author fxzjshm opened on May 4, 2022
  2

• Do not generate DDR bank by default if there is no DDR but HBM

  bug
  triSYCL/sycl#176 · Filter by author keryell opened on Apr 29, 2022
  5

  

• fpga_hls_hw_emu fails in vpl step

  bug
  triSYCL/sycl#168 · Filter by author j-stephan opened on Mar 2, 2022
  9

• Simplify difference in clang/test/CodeGenSYCL/loop_unroll.cpp

  triSYCL/sycl#159 · Filter by author keryell opened on Jan 27, 2022
  1

  

• Handling also sycl::ext::xilinx

  enhancement
  triSYCL/sycl#157 · Filter by author keryell opened on Jan 27, 2022
  

• Adding more small examples from old triSYCL to compare with HLS

  triSYCL/sycl#149 · Filter by author keryell opened on Oct 23, 2021
  

• xilinx::pipeline_kernel not compiling

  triSYCL/sycl#148 · Filter by author keryell opened on Oct 23, 2021
  2

  

• Option -fsycl-unnamed-lambda is no longer working

  bug
  triSYCL/sycl#145 · Filter by author keryell opened on Oct 22, 2021
  3

  

• Push signed 1-bit integer into C/C++ standard

  enhancement
  triSYCL/sycl#141 · Filter by author keryell opened on Oct 13, 2021
  3

  

• xilinx::pipeline not providing performance

  triSYCL/sycl#136 · Filter by author ShanoToni opened on Sep 17, 2021
  6

• Multiple accessor to the same buffer with different ddr_bank property doesn't work

  bugenhancement
  triSYCL/sycl#135 · Filter by author lforg37 opened on Sep 16, 2021
  1

  

• Rename various symbols to latest Xilinx tools

  triSYCL/sycl#122 · Filter by author keryell opened on May 25, 2021
  

• -Werror breaks toolchain compilation with clang

  bug
  triSYCL/sycl#108 · Filter by author j-stephan opened on Feb 5, 2021
  4

• Testing sycl/unified/next branch with path_tracer

  enhancement
  triSYCL/sycl#106 · Filter by author keryell opened on Feb 5, 2021
  

• Add more Xilinx FPGA examples from Xilinx/HLS-Tiny-Tutorials

  enhancement
  triSYCL/sycl#104 · Filter by author keryell opened on Dec 14, 2020

• Update /llvm/sycl/doc/Tests.md

  triSYCL/sycl#85 · Filter by author keryell opened on Sep 29, 2020
  

• llvm/sycl/test/xocc_tests/disabled/edge_detection example does not work

  bug
  triSYCL/sycl#83 · Filter by author keryell opened on Sep 29, 2020
  3

  

• [SYCL] hls's libspir contains unoptimized IR and some buggy IR

  bug
  triSYCL/sycl#78 · Filter by author Ralender opened on Sep 14, 2020
  4

• [SYCL][Driver] Refactor xocc driver script back into the LLVM Driver/ToolChain

  enhancementquestion
  triSYCL/sycl#73 · Filter by author agozillon opened on Nov 8, 2019

• How to specify host compiler for xocc?

  question
  triSYCL/sycl#68 · Filter by author j-stephan opened on Sep 18, 2019
  3