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fix(platform): centralize cache-line sizing - #831
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Define overridable AILEGO_CACHE_LINE_SIZE with a 128-byte Apple ARM64 default and a 64-byte default elsewhere. Use it for prefetch strides and budgets, cache isolation, aligned buffers, and in-memory vector layouts. Preserve fixed SIMD widths and on-disk layouts. Keep zero-line prefetch a no-op and retain caller-side automatic line counts. Update parameter documentation and alignment/prefetch regression tests, including the latest Flat query-metadata cache isolation. Validation: 170 regression tests on upstream/main (8397071), covering platform helpers, allocation, buffer storage, HNSW, Vamana, and Flat.
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Define overridable AILEGO_CACHE_LINE_SIZE with a 128-byte Apple ARM64 default and a 64-byte default elsewhere. Use it for prefetch strides and budgets, cache isolation, aligned buffers, and in-memory vector layouts. Preserve fixed SIMD widths and on-disk layouts.
Keep zero-line prefetch a no-op and retain caller-side automatic line counts. Update parameter documentation and alignment/prefetch regression tests, including the latest Flat query-metadata cache isolation.
Validation: 170 regression tests on upstream/main (8397071), covering platform helpers, allocation, buffer storage, HNSW, Vamana, and Flat.